Principal Engineer Functional Verification (f/m/div) - #2117805

Join our team as a Principal Engineer Functional Verification and develop and implement verification strategies, driving innovation in IP and SOC verification in an ASIL environment. Collaborate with cross-functional teams, design and develop System Verilog UVM-based components, and take your career to the next level.

Job Description

In your new role you will:

• Develop and implement verification strategy and supervise team members
• Be a hands-on contributor to IP & SOC verification in ASIL Environment, either from scratch or by leveraging existing verification environments and flows
• Collaborate with IP designers, verification and software teams to gather, define, and refine verification requirements and develop and review verification plans
• Effectively collaborate with the broader technical community, for continuous learning and sharing best practices across teams
• Design and develop System Verilog UVM-based components and environments
• Analyze and enhance regressions and functional coverage to achieve 100% coverage
• Improve development methodologies with a focus on reuse and efficiency gains, fostering innovation
• Lead an international Team of Interns and external Consultants as Verification Lead
• Be responsible and accountable for your own deliverables as well as for the entire Team, on-time and with quality
  
  

Your Profile

As a Principal Engineer Functional Verification, you set yourself ambitious goals. Furthermore, work conscientiously on making things better, faster, and more efficient. Lastly, are able to quickly establish a successful cooperation.

You are best equipped for this task if you have:

• A degree in Electrical Engineering or similar field
• At least 6 years of Design Verification experience
• A minimum of 4 years of experience in ASIL D environment
• Deep expertise in verification environments development and all verification tasks needed to achieve design verification closure
• Deep knowledge of System Verilog and UVM verification methodology
• Strong ability to solve complex technical problems
• Fluent English communication skills, preferably good in German
  
  

Contact:

Carolina Moreira, LinkedIn

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