Staff Verification Engineer, Interface IP - #2085640

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

An experienced and highly skilled Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.

What You’ll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Creating and executing detailed test plans to verify complex ASIC designs.
• Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Staying current with the latest verification methodologies and tools to continually improve processes.
• Mentoring and guiding junior verification engineers in best practices and methodologies.
  
  

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.
  
  

What You’ll Need:

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols.
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Experience with simulation tools such as VCS or similar.
• Excellent problem-solving skills and attention to detail.
  
  

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• Mentor and leader, capable of guiding and developing junior engineers.
  
  

The Team You’ll Be A Part Of: You will join a dedicated team of engineers focused on the design and verification of high-performance digital ASICs. Our team is committed to innovation, quality, and excellence, working collaboratively to push the boundaries of technology. We value continuous learning and professional growth, providing ample opportunities for development and advancement.